1. Field of the Invention
The present invention relates to a liquid crystal display device and a driving method of the same, and more particularly, to a timing controller of a driving circuit for an LCD device and a driving method of the same.
2. Discussion of the Related Art
Liquid crystal display (LCD) devices have been widely used for monitors of personal computers or notebook computers, personal digital assistants (PDAs) and wall-mounted televisions because of their thin thickness, light weight and low power consumption.
A related art LCD device will be described in more detail with reference to accompanying drawings.
FIG. 1 is a view of schematically illustrating a related art LCD device. In FIG. 1, the LCD device includes a liquid crystal panel 10 and a driving system 20. The liquid crystal panel 10 displays images, and the driving system 20 generates and provides signals for driving elements of the liquid crystal panel 10.
The liquid crystal panel 10 includes gate lines 12 and data lines 14 that cross each other and define pixel regions. A thin film transistor T, a liquid crystal capacitor CLC and a storage capacitor CST are disposed in each pixel region. The thin film transistor T is connected to the gate and data lines 12 and 14. The liquid crystal capacitor CLC and the storage capacitor CST are connected to the thin film transistor T.
The driving system 20 includes a timing controller 22, a gate driver 24 and a data driver 26. RGB data and control signals are input from an external system (not shown) to the timing controller 22. The timing controller 22 re-arranges the RGB data and generates gate control signals and data control signals for controlling the gate driver 24 and the data driver 26, respectively. The timing controller 22 provides the gate driver 24 with the gate control signals and the data driver 26 with the data control signals and the re-arranged RGB data.
The gate driver 24 supplies gate signals VG to the gate lines 12 of the liquid crystal panel 10 according to the gate control signals from the timing controller 22. The data driver 26 provides data signals Vdata to the data lines 14 of the liquid crystal panel 10 according to the data control signals and the RGB data from the timing controller 22.
Therefore, the liquid crystal panel 10 displays images in accordance with the gate signals VG and the data signals Vdata.
The timing controller 22 is connected to the external system through an interface, and the RGB data and the control signals are transmitted through a transistor-transistor logic (TTL) signaling. However, since a large number of transmission paths are necessary to transmit the RGB data and the control signals through the TTL signaling, a large number of cables and connectors are also needed. Accordingly, the transmission paths are more easily exposed to external noises, and the RGB data and the control signals are directly or indirectly influenced by the external noises, whereby images may be abnormally displayed.
To solve such a problem, a low voltage differential signaling (LVDS) has been proposed for the interface. The LVDS is a high-speed digital interface technology, in which two different voltages having opposite polarities are generated and data is transmitted by comparing the voltages. Accordingly, the data can be transmitted at low voltages, and the LVDS has advantages of low power consumption and high transmission speed. In addition, the LVDS is relatively highly resistant to the external noises.
A related art timing controller using the LVDS technology will be described in detail with reference to accompanying drawings.
FIG. 2 and FIG. 3 are views of schematically illustrating a related art timing controller. FIG. 2 shows connections of the timing controller with other systems, and FIG. 3 shows a structure of the timing controller.
In FIG. 2 and FIG. 3, the timing controller 30 includes a LVDS receiver (LVDS Rx) 32 and a logic unit 34.
The LVDS receiver 32 is connected to a LVDS transmitter (LVDS Tx) 40. The LVDS receiver 32 includes a phase locked loop (PLL) 32a. The PLL 32a keeps phases of output signals and input signals uniform.
The logic unit 34 is connected to gate and data drivers 54 and 56. The logic unit 34 includes a fail safe 34a, a gate control signal generator 34b, a data control signal generator 34c and a data processor 34d. 
The LVDS transmitter 40 converts RGB data and control signals into a LVDS-type. The LVDS transmitter 40 provides the LVDS receiver 32 with the LVDS-type signals. The control signals includes a vertical sync signal Vsync, a horizontal sync signal Hsync, a data enable signal DE and a clock signal CLK.
Next, the LVDS receiver 32 converts the LVDS-type signals into a TTL-type and provides the logic unit 34 with the TTL-type signals.
The gate control signal generator 34b and the data control signal generator 34c, respectively, generate gate control signals and data control signals according to the TTL-type signals and supply them to the gate and data drivers 54 and 56. In addition, the data processor 34d re-arranges the TTL-type RGB data and provides the re-arranged RGB data to the data driver 56.
Here, the gate control signals include a gate start pulse (GSP), a gate output enable (GOE) and a gate shift clock (GSC). The data control signals include a source output enable (SOE), a source sampling clock (SSC), a polarity reverse (POL) and a source start pulse (SSP).
The fail safe 34a decides whether signals from the LVDS receiver 32 are normal or abnormal and controls abnormal operations of the gate control signal generator 34b, the data control signal generator 34c and the data processor 34d. When abnormal signals are input, the fail safe 34a gets a black image displayed on the liquid crystal panel 10 of FIG. 1.
FIG. 4 is a timing chart showing input and output signals of a related art timing controller. FIG. 4 shows output gate start pulse GSP and gate shift clock GSC according to input clock signal CLK and data enable signal DE. Here, a frame frequency is fixed at 60 Hz.
In FIG. 4, signals are input and output at each of frames F1 and F2. The clock signal CLK and the data enable signal DE are input to the timing controller 30 of FIG. 2 from an external system (not shown). The gate start pulse (GSP), the gate shift clock (GSC) and other control signals (not shown) are generated according to the clock signal CLK and the data enable signal DE and are input to the gate driver 54 of FIG. 2.
There exists a vertical blanking interval VBI between first and second frames F1 and F2, that is, between after outputting data corresponding to a last gate line of the first frame F1 and before inputting data corresponding to a first gate line of the second frame F2. During the vertical blanking interval VBI, data is not applied.
As stated above, the LCD device has been used for various devices, and portable devices have limitations on using time because images are displayed within restricted power. Recently, various methods have been sought to increase the using time by reducing power consumption. As one of these methods, a method of displaying images with a low frame frequency has been proposed by decreasing the frame frequency during the vertical blanking interval VBI in case that the images are not moving pictures or moving images, for example, still images.
However, when the frame frequency is changed, flickering of the images may occur.
Table 1 shows measurements of display states when the frame frequency is changed according to the related art. Here, a setting time means a point when the frame frequency is changed, and a measuring time indicates a point when the display states are measured. At this time, a point when a frame finishes is used as a reference. Accordingly, the setting time corresponds to a period between the point when the frame frequency is changed. The measuring time corresponds to a period between the point when the previous frame finishes and the point when the display states are measured.
TABLE 1interval0151020304050607080100Setting4041□s45□s50□s60□s70□s80□s90□s100110120140time□s□s□s□s□sMeasuring—68□s74-8880-9690-106100-114110-126122-134134-148148-158158-170176time□s□s□s□s□s□s□s□s□s□sDisplay state—abnormalabnormalabnormalabnormalabnormalabnormalabnormalabnormalabnormalabnormalabnormal
As shown in Table 1, in the related art, when the frame frequency is changed, abnormal images are displayed.
A more detail explanations follows with reference to FIG. 5.
FIG. 5 is a timing chart showing input and output signals of a timing controller when a frame frequency is changed according to the related art. The frame frequency is changed from 60 Hz to 40 Hz. FIG. 5 shows the data enable signal output from the LVDS receiver 32 of FIG. 3, which is referred to as output DE hereinafter, and the gate control signals GSP and GSC output from the logic unit 34 of FIG. 3 according to the clock signal CLK and the data enable signal input to the LVDS receiver 32 of FIG. 3, which is referred to as input DE hereinafter.
In FIG. 5, the frame frequency can be changed during the vertical blanking interval as occasion demands, and for example, the frame frequency may be changed from 60 Hz to 40 Hz.
At this time, a frequency of the clock signal CLK is also changed, and the PLL 32a of FIG. 3 of the LVDS receiver 32 of FIG. 3 is unlocked. More particularly, the PLL 32a of FIG. 3 generates a signal that has a fixed relation to a phase of a reference signal. The PLL 32a of FIG. 3 compares a frequency of an output signal with a frequency of an input signal by using feedback of the output signal and locks the frequency of the output signal when the frequency of the output signal is the same as the frequency of the input signal. By the way, when the frequency of the clock signal CKL is changed, the frequency of the output signal is different from the frequency of the input signal. Therefore, the PLL 32a of FIG. 3 unlocks the frequency of the output signal, and a predetermined time is needed until the frequency of the output signal is fixed at the changed frequency. Accordingly, the output DE from the LVDS receiver 32 of FIG. 3 is not parallelized with the input DE to the LVDS receiver 32 of FIG. 3 and has an unknown state. Accordingly, the output DE has a glitch.
The output DE having the glitch is input to the logic unit 34 of FIG. 3, and since the control signals are generated on the basis of such an output DE, the control signals also have unknown states. Therefore, the gate control signals such as the gate start pulse GSP or the gate shift clock GSC may be unknown. This causes flickering of the images, and a black image is disposed by the fail safe 34a of FIG. 3.